(a) Field of the Invention
The present invention relates to a field emission: display and, more particularly, to a field emission display which maximizes electron emission density of a field emitter while minimizing damage of the field emitter due to over-current.
(b) Description of the Related Art
Generally, field emission displays (FEDs) are display devices where electrons are liberated from an emitter on a cathode by quantum mechanical tunneling and impinge upon phosphors on an anode, thereby producing a predetermined screen image.
A micro-tip based field emitter is typically used for such an emitter for the field emission display. The field emission display includes a faceplate anode substrate with a bottom surface, and a backplate cathode substrate with a top surface facing the bottom surface of the faceplate substrate. The top surface of the backplate substrate is sequentially overlaid with a cathode electrode layer and a gate electrode layer such that the electrode layers intersect orthogonal to each other. An insulation layer is interposed between the cathode electrode layer and the gate electrode layer to electrically insulate them from each other. The portions of the insulation layer and the gate electrode layer where the cathode electrode layer and the gate electrode layer intersect are etched to thereby form a large number of holes for accommodating micro-tips for the emitter. Meanwhile, the bottom surface of the faceplate substrate is sequentially overlaid with an anode electrode layer and a phosphor layer.
In the above-structured field emission display, electric field is formed around the micro-tip emitter due to voltage difference applied to the cathode electrode layer and the gate electrode layer. Electrons are liberated from the micro-tips under the influence of the electric field, and accelerated toward the phosphor layer by high voltage applied to the anode electrode layer, thereby striking the phosphors on the phosphor layer.
In the meantime, under the application of over-current, the micro-tips for the emitter are liable to breakdown, causing device failure. In this connection, several techniques for protecting the emitter have been suggested.
For instance, U.S. Pat. No. 4,940,916 discloses a technique of interposing a resistance layer between the cathode electrode layer and the micro-tips for the field emitter. The resistance layer functions as a butter resistor for protecting the micro-tips.
However, in such a technique, the resistance layer should be formed on the entire surface of the cathode electrode layer, and this structure makes it difficult to control suitable resistance degree of the resistance layer for preventing breakdown of the emitter.
Japanese Patent No. 9-92131 discloses another technique of protecting the micro-tip emitter. As shown in FIGS. 9 and 10, non-electrode portions 7 are formed in the cathode electrode layer 5, and an inner island-like electrode 9 is formed within each non-electrode portion 7. The cathode electrode layer 5, the non-electrode portions 7 and the island-like electrodes 9 are covered by a resistance layer 11. A plurality of cone-shaped micro-tips are arranged on the resistance layer 11 such that they are placed within the area corresponding to the location of each island-like electrode 9.
In the above structure, the density of current applied to the emitter 13 can be controlled through the resistance layer 11. Furthermore, the resistance degree of the resistance layer 11 can be controlled by; varying the distance between the cathode electrode layer 5 and the island-like electrode 9.
However, it is difficult to employ the above-structured field emission display for use in the large-sized high resolution display device application. When the width of the cathode electrode layer is reduced to realize high resolution screen image, the width of the island-like electrode 9 is reduced as much, and resistance at that position increases. In this structure, it naturally follows that the number of the micro-tips 13 to be formed over the narrowed island-like electrode 9 should be limited, and high resolution of the display device cannot be realized. In addition, when the display device becomes large-sized, the portion of the narrowed island-like electrode 9 with increased resistance is lengthened so that the desired resistance degree cannot be obtained.
It is an object of the present invention to provide a field emission display which can effectively protect a field emitter from entering into breakdown while bearing sufficient display area for realizing high resolution.
It is another object of the present invention to provide a field emission display which can prevent voltage drop at a cathode electrode layer with an increased length.
These and other objects may be achieved by a field emission display including first and second substrates spaced apart from each other with a predetermined distance. The top surface of the first substrate faces the bottom surface of the second substrate. A main cathode electrode layer is disposed on the top surface of the first substrate. A gate electrode layer is arranged over the main cathode electrode layer such that the gate electrode layer and the main cathode electrode layer intersect to be orthogonal to each other. The intersection of the gate electrode layer and the main cathode electrode layer becomes to be unit pixel areas. The gate electrode layer has a plurality of holes at the unit pixel areas.
A resistance layer is formed on the main cathode electrode layer while being positioned at the unit pixel areas. A first insulation layer with one or more contact holes is formed on the resistance layer. A subsidiary cathode electrode layer is formed on the first insulation layer while contacting the resistance layer through the contact holes. A second insulation layer is formed on the subsidiary cathode electrode layer. The gate electrode layer is formed on the second insulation layer. A field emitter with a plurality of electron emitting members is positioned within the holes of the gate electrode layer while resting on the subsidiary cathode electrode layer.
An anode electrode layer is formed on the bottom surface of the second substrate with a predetermined electrode pattern. A phosphor layer is formed on the anode electrode layer.
The main cathode electrode layer is provided with a plurality of linear electrodes, a plurality of non-electrode portions formed at each linear electrode, and one or more island-like electrodes positioned within each non-electrode portion while being spaced apart from the linear electrode with a predetermined distance.
Alternatively, the island-like electrodes may be formed on the subsidiary cathode electrode layer with a suitable structure.